It has been mainly employed, as a resistor for a semiconductor device, a diffusion resistor which uses a diffusion layer formed in a semiconductor substrate as a resistor The diffusion resistor is constituted in such a manner that boron is doped to a surface portion of, for example, an n-type epitaxial layer to form a p+ diffusion region, then electrodes (e.g., Al electrodes and so on) are formed at opposite ends of the diffusion region.
In recent years, a polycrystalline silicon resistor which uses a polycrystalline silicon film as a resistor has been employed. The polycrystalline silicon resistor is constituted in a manner as shown in FIG. 6 that a polycrystalline silicon film 3 including impurities serving as a resistor is formed on a field insulating layer (SiO.sub.2 layer) 2 formed on a major surface of a silicon substrate 1, thereafter an SiO.sub.2 layer 4 is deposited on the entire surface of the polycrystalline silicon film 3 by the chemical vapor deposition (CVD) process, then a pair of Al electrodes (interconnections) 6 are formed on opposite ends of the polycrystalline silicon film 3 through contact holes. Thus constructed polycrystalline silicon resistor 7 has the following features when compared with the above-described diffusion resistor:
(i) the diffusion resistor has such a property that a resistance value changes depending on a depletion layer, so-called back bias dependence, since a junction is separated by applying a reverse bias voltage between it and the neighboring semiconductor region, while the polycrystalline silicon resistor 7 does not have such a back bias dependence; PA1 (ii) the diffusion resistor has such a property that an expansion of a depletion layer is changed depending on a voltage applied thereto to thereby change a resistance value, so-called self bias dependence, while the polycrystalline silicon resistor 7 does not have such a self bias dependence; PA1 (iii) the diffusion resistor is changed in its resistance value depending on the orientation of a wafer and by the influence of stress applied thereto in the assembling-process (e.g., in the molding process), while the polycrystalline silicon resistor 7 is not influenced in its resistance value by the orientation of a wafer and little influenced by the stress in the assembling process; and PA1 (iv) the polycrystalline silicon resistor is more advantageous in the temperature characteristics.
Now, as one of bipolar transistors, there has been proposed a ultra-high speed bipolar transistor which is constructed in a manner that both a base leading-out electrode and an emitter leading-out electrode are formed by a polycrystalline silicon film, then a base region and an emitter region are formed in a self-alignment fashion by diffusing impurities from the polycrystalline silicon film serving as the emitter leading-out electrode. FIG. 8 illustrates an example of methods of manufacturing the ultra-high speed bipolar transistor. As shown in FIG. 8A, on a major surface of a first conductivity type, e.g., p-type silicon substrate 11, a second conductivity type, e.g., n-type collector buried region 12 and a p-type channel stopper region 13 are formed, then an n-type epitaxial layer 14 is grown thereon. Thereafter, a highly-doped n-type collector leading-out region 15 reaching to the collector buried region 12 is formed, and a field insulating film 16 is formed by the local oxidation on the regions except for the collector leading-out region 15 and a region 14A on which base and collector regions are formed in the succeeding processes. Then, a thin insulating layer, e.g., SiO.sub.2 layer 17 is formed on an entire surface thereof, and a portion thereof corresponding to the region 14A is opened to form a first polycrystalline silicon layer 18 serving as a base leading-out electrode by the CVD process, then boron acting as p-type impurities is doped to the polycrystalline silicon film 18. Thereafter, the p+ polycrystalline silicon film 18 is subjected to the patterning process by a first resist mask 19 having a pattern corresponding to the external configuration of the base leading-out electrode.
Referring to FIG. 8B, an SiO.sub.2 film 20 is deposited by the CVD process on an entire surface including the p+ polycrystalline silicon film 18 having been subjected to the patterning process, and thereafter a second resist mask 21 is formed thereon. A part of the SiO.sub.2 film 20 and the P+polycrystalline silicon film 18 corresponding to an active portion so as to form an intrinsic base region and an emitter region is selectively removed by the etching-process through the resist mask 21 to thereby form an opening 23 and also to form a base leading-out electrode 22 formed of the p+ polycrystalline silicon film 18.
Then, as shown in FIG. 8C, p-type impurity boron is implanted by the ion implantation technique through the opening 23 to form a link base region 24 on the region 14A for connecting an external base region and the intrinsic base region which are to be formed. An SiO.sub.2 film is then deposited by the CVD process and the above deposited SiO.sub.2 film by the CVD is densified by the heat treatment at about 900.degree. C. Due to the heat treatment at this time, the impurity boron from the base leading-out electrode 22 of the P.sup.+ polycrystalline silicon film is diffused to form a part of an external base region 26. Then, by the etch back-process a side wall 25 of SiO.sub.2 is formed at the inner wall of the base leading-out electrode 22 facing to the opening 23.
Thereafter, as shown in FIG. 8D, a second polycrystalline silicon film 28 finally serving as the emitter leading-out electrode is formed by the CVD process at an opening 27 defined by the side wall 25, and p-type impurity (e.g., B or BF.sub.2) is implanted by the ion implantation process into the polycrystalline silicon film 28 which is in turn annealed to form a p-type intrinsic base region 29 at the active portion, then n-type impurity (e.g., arsenic) is implanted into the film by the ion implantation process and annealed to form an n-type emitter region 30. The p-type intrinsic base region 29 and the n-type emitter region 30 may be formed instead of the above-described method in a manner that the p-type impurity and the n-type impurity are sequentially implanted into the polycrystalline silicon film 28 by the ion implantation process and simultaneously annealed. Due to the annealing-process, for forming the base and emitter electrodes, the impurity boron from the base leading-out electrode 22 of the P.sup.+ polycrystalline silicon film is diffused to finally form the external base region 26. Now, the intrinsic base region 29 is higher in the impurity density than that of the link base region 24. Thereafter, contact holes are formed, and then a base electrode 31, a collector electrode 32 and an emitter electrode 33 are formed by metal (e.g., Al), thereby constituting a ultra-high speed bipolar transistor 34.
The above-described polycrystalline silicon resistor is used in a ultra-high speed bipolar LSI, Bi-CMOS LSI etc. including the above-described ultra-high speed bipolar transistor.
However, since the above-described polycrystalline silicon resistor is formed on the field insulating layer 2, a step becomes larger, whereby interruption of the step and electromigration may occur at the Al electrode (interconnection) 6 of the upper layer due to the coverage of the CVD SiO.sub.2 film 4 at a step portion A in FIG. 6. Further, since the CVD SiO.sub.2 film 4 at the step portion A is fragile from a film quality standpoint, when the Al interconnection 8 crosses over the resistor 7 as shown in FIG. 7, a leak current may be generated between the polycrystalline silicon resistor 7 and the Al interconnection 8 at a step portion B.
The reason that the quality of the CVD SiO.sub.2 film 4 is degraded is considered as follows. Namely, when the polycrystalline silicon film 3 to be the resistor is subjected to the patterning process by, for example, the reactive ion etching (RIE) process through the resist mask, a surface of the field insulating layer 2 is damaged, and a surface of the polycrystalline silicon film 3 is polluted and damaged when the ashing of the resist mask is performed, so that the CVD SiO.sub.2 film 4 formed on the polycrystalline silicon film becomes thin in thickness and becomes fragile.
Now, in the case of the polycrystalline silicon resistor, a sheet resistance value thereof can be controlled in accordance with the kinds of impurities and an amount of dose when the thickness thereof is fixed. However, even though boron (B), arsenic (As) and phosphor (P) etc., have various characteristics, but each of these impurities has such a common tendency that when an amount of dose of the impurities is increased more than a predetermined value, a sheet resistance value is not decreased but increased due to the segregation of the impurities, etc. FIG. 4 is a graph illustrating dependence of the sheet resistance on an amount of dose of boron, wherein a curve a.sub.2 shows a conventional case. FIG. 5 is a graph illustrating dependence of the sheet resistance on an amount of dose of arsenic or phosphor, wherein a curve b.sub.2 shows a conventional case. As is clear from these drawings, it has been difficult to obtain a low resistance value by using the polycrystalline silicon resistor with a thin film (which is normally used to obtain a high resistance value).
Accordingly, in view of the above-described drawbacks of the conventional manufacturing method, an object of the present invention is to provide a method of manufacturing semiconductor devices which is capable of forming a stable insulating film with a good quality and forming a resistor with high reliability which does not cause an interruption of a step of electrodes and interconnections or a leak current between the resistor and the interconnections.
Another object of the present invention is to provide a method of manufacturing semiconductor devices which is capable of obtaining a resistor with a lower resistance value in a highly dosed region.